Skip to content
  • Home
  • MIP Systems
    • MIP | Plasma Decapsulation
    • MIP+ | Plasma Die-Level Etching
  • Solutions
    • IC decapsulation
  • Applications
  • Publications
    • Publications
    • News
  • Events
  • About us
    • About us
    • Contact
  • Home
  • MIP Systems
    • MIP | Plasma Decapsulation
    • MIP+ | Plasma Die-Level Etching
  • Solutions
    • IC decapsulation
  • Applications
  • Publications
    • Publications
    • News
  • Events
  • About us
    • About us
    • Contact
GET IN TOUCH

Hardware Security Evaluation of Advanced Packaging

Exposed EEPROM on PCB after MIP Decapsulation

Nanyang Technological University, ISTFA 2025, Die & Data Extraction, PCB, SiP, Cu Bond Wire.

Delft, The Netherlands
+31 625 261 648

[email protected]

MIP

MIP+

IC Decapsulation

Applications

Publications

About us

News

Job openings

Contact

Privacy declaration