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2.5D sample preparation with MIP decapsulation

MIP decapsulation is an effective sample preparation method for advanced 2.5D and 3D semiconductor packages, enabling precise underfill removal without damaging Cu microbumps or critical features. Unlike acid or conventional plasma methods, it avoids corrosion, preserves failure sites, and delivers significantly faster etching rates—supporting accurate and efficient failure analysis.

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Be sure to catch JIACO Instruments presenting & exhibiting in May

During May, you will have the opportunity to learn from JIACO Instruments at several leading conferences and exhibitions we will be attending. Be sure to note the following presentation dates during these conferences to discover our latest applications and solutions: RadNext Workshop – held in Rome, ItalyOn May 6th, our colleague Yashan Peng-Shan Peng will

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Detecting subtle wire bond defects with MIP decapsulation

Undetected wire bond defects can lead to intermittent faults or premature device failure, even when samples pass electrical curve trace analysis. JIACO Instruments’ MIP decapsulation offers a faster way to uncover these subtle issues, as minor bonding defects become visible through simple optical inspection. In a recent case study, an electrically failing PCC sample revealed oxidised, rough-surfaced defective bonds after MIP processing—providing clear visual evidence that traditional decapsulation methods can miss.

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Passivation crack SiC High Tg Mold compound after MIP decap

Manuscript featuring MIP selected as an Editor’s Choice article for2025 from the Journal of Failure Analysis and Prevention.

Congratulations to Mr. Sorrells, Mr. Nielsen, Mr. Walters of Microchip Technology and Dr. Tang, and Mr. McKinnon of JIACO Instruments, who have received confirmation that their manuscript “Optimizations and Case Studies: Decapsulation of Hardened Epoxy SiC MOSFETs and Diodes via JIACO Microwave-Induced Plasma Etching” was selected as an Editor’s Choice article for 2025 from the

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Enabling preservation and full exposure of EOS failure sites by MIP

Electrical overstress (EOS) occurs when the voltage, current, or power in the device exceeds some maximal limit, inducing thermal damage in the device. This is one of the most common types of electrical failures, found in all stages of the IC device life cycle. Determining the root cause of EOS is integral to prevent future

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