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Enabling preservation and full exposure of EOS failure sites by MIP

Electrical overstress (EOS) occurs when the voltage, current, or power in the device exceeds some maximal limit, inducing thermal damage in the device. This is one of the most common types of electrical failures, found in all stages of the IC device life cycle. Determining the root cause of EOS is integral to prevent future

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๐—›๐—ถ๐—ด๐—ต ๐—ง๐—ด ๐—ฒ๐—ฝ๐—ผ๐˜…๐˜† ๐—บ๐—ผ๐—น๐—ฑ ๐—ฐ๐—ผ๐—บ๐—ฝ๐—ผ๐˜‚๐—ป๐—ฑ๐˜€ ๐—ฎ๐—ฟ๐—ฒ ๐˜„๐—ถ๐—ฑ๐—ฒ๐—น๐˜† ๐˜‚๐˜€๐—ฒ๐—ฑ ๐—ณ๐—ผ๐—ฟ ๐—ต๐—ถ๐—ด๐—ต-๐˜๐—ฒ๐—บ๐—ฝ๐—ฒ๐—ฟ๐—ฎ๐˜๐˜‚๐—ฟ๐—ฒ ๐—ฎ๐—ฝ๐—ฝ๐—น๐—ถ๐—ฐ๐—ฎ๐˜๐—ถ๐—ผ๐—ป๐˜€ ๐˜€๐˜‚๐—ฐ๐—ต ๐—ฎ๐˜€ ๐—ฎ๐˜‚๐˜๐—ผ๐—บ๐—ผ๐˜๐—ถ๐˜ƒ๐—ฒ ๐—ฒ๐—น๐—ฒ๐—ฐ๐˜๐—ฟ๐—ผ๐—ป๐—ถ๐—ฐ๐˜€.

A known challenge is preserving copper bond wires during decapsulation, as conventional acid processes can damage the wires. This becomes even more critical when silver-plated leadframes are used, since acid and conventional plasma etching readily attack silver and make stitch bond exposure difficult. This work, by Sumitomo Bakelite, presents a decapsulation process based on Microwave

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Lookingย back on 2025ย andย happyย holidays!ย ย 

2025 has been a meaningful year for JIACO Instruments in many ways.ย  Weย commemorateย the passing of our co-founder, Prof. Keesย Beenakker. His pioneering work and the inspiration he shared with colleagues continue to shape the MIP and guide JIACO Instruments into the future.ย  We’reย proud of our achievements in 2025, including: – Plenary talk byย Prof.ย Keesย Beenakkerย at ICEPT 2025ย  –

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๐— ๐—œ๐—ฃ: ๐—ฃ๐—ฒ๐—ฟ๐—ณ๐—ฒ๐—ฐ๐˜ ๐—ณ๐—ผ๐—ฟ ๐—ฟ๐—ฒ๐—น๐—ถ๐—ฎ๐—ฏ๐—ถ๐—น๐—ถ๐˜๐˜† ๐˜๐—ฒ๐˜€๐˜๐—ถ๐—ป๐—ด

Conventional acid decapsulation is well known to damage copper wire bonds, leading to artificially low Cpk values that do not represent the original sample condition. This effect becomes more severe for wire diameters below 25 um and when high Tg mold compounds are used. Acid processes can also leave residues on the die surface, damage

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๐—๐—œ๐—”๐—–๐—ข ๐—œ๐—ป๐˜€๐˜๐—ฟ๐˜‚๐—บ๐—ฒ๐—ป๐˜๐˜€โ€™ ๐—œ๐—ฆ๐—ง๐—™๐—” ๐Ÿฎ๐Ÿฌ๐Ÿฎ๐Ÿฑ ๐—ฟ๐—ฒ๐—ฐ๐—ฎ๐—ฝ

The JIACO Instruments sales & applications teams have returned from a busy and insightful ISTFA 2025 where we met with many existing & potential customers on how we can support their localised decapsulation & etching challenges. ย  This year ISTFA focused on advanced packaging, with the AMD keynote underlining a key trend in the growth

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๐—œ๐—ฆ๐—ง๐—™๐—” ๐Ÿฎ๐Ÿฌ๐Ÿฎ๐Ÿฑ: ๐—ง๐—ผ๐—ผ๐—น๐˜€ ๐—ผ๐—ณ ๐˜๐—ต๐—ฒ ๐—ง๐—ฟ๐—ฎ๐—ฑ๐—ฒ!ย 

This Monday (17th of November), our colleaguesย Sarah Zeroualiย andย Mark McKinnonย presented โ€The Tools of the Tradeโ€ atย JIACO Instrumentsย booth (#715). They introduced ISTFAโ€™s attendees to the MIP and MIP+ machines and their applications, by highlighting two customer papers,ย which will be presented during ISTFA 2025. Brandon Capelliniย fromย Analog Devicesโ€˜ paper on Efficient Preparation of GaAs devices utilizing JIACOโ€™s MIP decapsulation.

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