Abstract
The rapid development of advanced packaging technologies for high-performance computing (HPC) applications poses
significant challenges for sample preparation methodologies. Conventional techniques are often insufficient to cope with the complex architectures and heterogeneous materials of modern packages, such as COWOS (Chip-on-Wafer-on-Substrate) and 3D structures. In this paper, we present a novel approach for sample preparation that leverages precision CNC (Computer Numerical Control) milling and selective MIP plasma etch.
These methods enable precise and selective removal of unwanted material, while preserving the integrity of the target region of interest. We demonstrate the effectiveness of our approach on various advanced packages and show how it facilitates the failure analysis tasks for HPC chips.
Joseph Sanchez (NVIDIA. USA)
Chuan Zhang (NVIDIA. USA)
John Aguada (NVIDIA. USA)
Jane Li (NVIDIA. USA)
Jiaqi Tang (JIACO Instruments. Delft, The Netherlands)
Chris Richardson (Allied High Tech Products Inc. USA)
FIGURES
Visual highlights from the research and analysis presented in this publication.
Fig. 1 — Optical images of the device after further MIP etching
Fig. 2 — Optical images of the device post MIP etching
Fig. 3 — Optical images of the device just after the mechanical milling step
