Abstract
III-V power electronic devices are a growing industry as electric vehicles (EVs), power-demanding servers, and other high-power electronics become more prominent. The design of these devices can alter a failure analysis lab’s process flow
typically used on traditional silicon-based logic devices. One such obstacle is backside fault isolation (FI) through highly doped silicon wafers used in GaN-on-Si technologies. Backside fault isolation is critical for many electrical failure analyses so finding several approaches to enable this technique that fits current FA flows is desirable. Chemical and Focused Ion Beam (FIB) based approaches have been used to enable backside FI [1], [2].
This paper considers a plasma-based approach with two separate machines, a Microwave Induced Plasma spot etcher and a chamber based Reactive Ion Etch (RIE). Both utilize a Fluorine-based chemistry which is highly selective to the silicon vs the underlying GaN. The etches are used to selective remove the silicon to form a window to the underlying GaN material. Subsequent backside FI analyses are successfully followed by several other analyses.
Kevin Distelhurst (GlobalFoundries. USA)
Jim Densmore (Globalfoundries. USA)
Jiaqi Tang (JIACO Instruments. Delft, The Netherlands)
FIGURES
Visual highlights from the research and analysis presented in this publication.
Fig. 1 — EFI signals observed on a sample post window formation. (a) LSM image with a TIVA signal observed over a defective device. (b) PEM signals observed in a defective device
Fig. 2 — Cross-sectional SEM image of a metallic bridge (arrow) post FIB processing.
Fig. 3 — Optical image of a metallic bridge observed through the GaN stack after a window is opened in the silicon wafer
