FA Challenges and Case Study Exploration of Multidie Fan-Out Wafer Level Packages

AMD, ISTFA 2024, RDL, 2.5D, 3D, Chiplet.
RDL within the MIP decapsulation cycle

Abstract

The semiconductor industry is no longer driven purely by performance. Miniaturization, increased functionality, low latency and high bandwidth requirements are becoming more important. Furthermore, as Moore’s law scaling becomes more difficult and costly, innovations in packaging technologies through heterogeneous integration are being adopted rapidly to meet these demands. This paper discusses how defects in InFO (Integrated Fan-Out) wafer level multidie semiconductor packages can be successfully root caused and describes the challenges faced when doing failure analysis of such packages.

Bernice Zee (AMD. Singapore), Qiu Wen (AMD. Singapore), Syahirah Mohammad-Zulkifli (AMD. Singapore)

RDL within the MIP decapsulation cycle

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